1st Student's Major
Electrical and Computer Engineering and Technology
1st Student's College
Science, Engineering and Technology
Students' Professional Biography
Hojoon Lee (M’08) was born in Seoul, South Korea, in 1988. In 2007 he graduated in Internet Information Communication from Sunrin Internet High School, Seoul, South Korea and continued his education for a Bachelor of Science in Electrical Engineering from Minnesota State University Mankato. He worked in Integrated Circuit Fabrication laboratory as a student helper in Spring 2010, and was Teaching Assistant for EE480/580 Integrated Circuit Fabrication laboratory in Fall 2011, Mankato, MN. His interested areas are Solid State Physics, Quantum Physics & Optics, Optoelectronics, and Nanofabrication. Samuel C. Wood was born in Brooklyn Park, Minnesota in 1990. In 2008 he graduated from Champlin Park High School, Minnesota and is now attending Minnesota State University Mankato to pursuing a Bachelor of Science in Electrical Engineering. Sam has been part of a research group that conducts research in the areas of analog design and device fabrication. The research group's latest project is using reactive ion etching to create metal oxide field effect transistor. His areas interests are analog design, micro and nanofabrication, and biomedical engineering.
Mentor's Name
Muhammad Khaliq
Mentor's Email Address
muhammad.khaliq@mnsu.edu
Mentor's Department
Electrical and Computer Engineering and Technology
Mentor's College
Science, Engineering and Technology
Abstract
The integrated circuit (IC) is dominated by technology using Complementary Metal-oxide-Semiconductor Field-effect Transistor (CMOSFET). In order to put over 300 million transistors on silicon chip requires selective removal of material by Reactive Ion Etching (RIE) which ensures vertical cut thereby increasing packing density of devices on the chip. The gate insulator of CMOS devices plays a crucial role in its electrical performance. In this research gate insulator of MOSFET has been etched by state-of-art technique RIE and its physical and electrical properties have been measured. The gate insulator etching by RIE give rise to charge accumulation on the gate dielectric resulting in change in threshold voltage. Also early breakdown of MOS devices is a direct consequence of charge accumulation on gate dielectric during RIE process. The RIE etching was performed with Technics Series 85-RIE unit, and it was optimized in respect of power, pressure, and composition of gases to achieve less charge accumulation, and stable threshold voltage. The thickness of the gate insulator was measured by the Nanospec before and after etching. Charges accumulated on gate oxide were measured by HP 4280A which is a high frequency capacitance-voltage (CV) measurement system. Annealing of the RIE etched gate oxide were performed at suitable temperature to bring the charges to minimum level. Results of the research are presented in tables and figures.
Recommended Citation
Lee, Hojoon and Wood, Samuel
(2011)
"Optimization of Reactive Ion Etching (RIE) Parameters for Selective Removal of MOSFET Gate Dielectric and Evaluation of its Physical and Electrical Properties,"
Journal of Undergraduate Research at Minnesota State University, Mankato: Vol. 11, Article 5.
DOI: https://doi.org/10.56816/2378-6949.1027
Available at:
https://cornerstone.lib.mnsu.edu/jur/vol11/iss1/5
Creative Commons License
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