Event Title

Optimization of Reactive Ion Etching (RIE) Parameters for Selective Removal of MOSFET Gate Dielectric and Evaluation of its Physical and Electrical Properties

Location

CSU 204

Start Date

4-4-2011 9:00 AM

End Date

4-4-2011 10:30 AM

Student's Major

Electrical and Computer Engineering and Technology

Student's College

Science, Engineering and Technology

Mentor's Name

Muhammad A. Khaliq

Mentor's Department

Electrical and Computer Engineering and Technology

Mentor's College

Science, Engineering and Technology

Description

The integrated circuit (IC) is dominated by technology using Complementary Metal-oxide-Semiconductor Field-effect Transistor (CMOSFET). In order to put over 300 million transistor on silicon chip requires selective removal of material by Reactive ion etching (RIE) which ensures vertical cut thereby increasing packing density of devices on the chip. The gate insulator of CMOS devices plays a crucial role in its electrical performance. In this research gate insulator of MOS FET has been etched by state-of-art technique RIE and its physical and electrical properties have been measured. The gate insulator etching by RIE give rise to charge accumulation on the gate dielectric resulting in change in threshold voltage. Also early breakdown of MOS devices is a direct consequence of charge accumulation on gate dielectric during RIE process.

The gate oxide of different ticknesses was grown in the Microelectronics Fabrication laboratory located in Trafton S194-196. The RIE etching was performed with Technic RIE unit, and it was optimized in respect of power, pressure, and composition of gases to achieve less charge accumulation, and stable threshold voltage. The physical properties such as thickness of insulator before and after etching were measured by Ellipsometer and NanoSpec, and charges accumulated on gate oxide was measured by HP high frequency capacitance-voltage (C-V) measurement system. Annealing of the RIE etched gate oxide were performed at suitable temperature to bring the charges to minimum level. Results of the research are presented in tables and figures.

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Apr 4th, 9:00 AM Apr 4th, 10:30 AM

Optimization of Reactive Ion Etching (RIE) Parameters for Selective Removal of MOSFET Gate Dielectric and Evaluation of its Physical and Electrical Properties

CSU 204

The integrated circuit (IC) is dominated by technology using Complementary Metal-oxide-Semiconductor Field-effect Transistor (CMOSFET). In order to put over 300 million transistor on silicon chip requires selective removal of material by Reactive ion etching (RIE) which ensures vertical cut thereby increasing packing density of devices on the chip. The gate insulator of CMOS devices plays a crucial role in its electrical performance. In this research gate insulator of MOS FET has been etched by state-of-art technique RIE and its physical and electrical properties have been measured. The gate insulator etching by RIE give rise to charge accumulation on the gate dielectric resulting in change in threshold voltage. Also early breakdown of MOS devices is a direct consequence of charge accumulation on gate dielectric during RIE process.

The gate oxide of different ticknesses was grown in the Microelectronics Fabrication laboratory located in Trafton S194-196. The RIE etching was performed with Technic RIE unit, and it was optimized in respect of power, pressure, and composition of gases to achieve less charge accumulation, and stable threshold voltage. The physical properties such as thickness of insulator before and after etching were measured by Ellipsometer and NanoSpec, and charges accumulated on gate oxide was measured by HP high frequency capacitance-voltage (C-V) measurement system. Annealing of the RIE etched gate oxide were performed at suitable temperature to bring the charges to minimum level. Results of the research are presented in tables and figures.

Recommended Citation

Lee, Hojoon and Samuel C. Wood. "Optimization of Reactive Ion Etching (RIE) Parameters for Selective Removal of MOSFET Gate Dielectric and Evaluation of its Physical and Electrical Properties." Undergraduate Research Symposium, Mankato, MN, April 4, 2011.
http://cornerstone.lib.mnsu.edu/urs/2011/oral-session-02/2